As contemporary semiconductor devices continue to decrease in size, the increase in density of patterned metal features can significantly affect device performance. Capacitance between patterned metal features in a semiconductor device, both on a single metal layer and between metal layers, can adversely affect the performance of the semiconductor device. Increasing the separation between patterned metal features can reduce the adverse effects of mutual capacitance. However, separating patterned metal features can increase metal line lengths, which tends to adversely affect device performance and nullify the benefits provided by separating the metal lines.
Metal interconnects between metal layers can have a significant impact on device performance. Since the size and location of metal interconnects affect both the electrical characteristics and the size of a circuit, special circumstances must be considered when designing and fabricating metal layer interconnects. Specifically, tolerances in the size and alignment of vias can make connecting two metal layers very difficult. In the context of semiconductor devices, a via is a filled through-hole that electrically connects two metal layers. Typical vias have a width of about 0.35 to about 0.5 microns, comparable to the widths of typical metal lines. Since the vias are about the same size as the electrically connected metal lines, the vias must be formed to contact a metal line exactly. If exact contact is not made, the metal interconnects can violate a minimum required spacing between metal lines specified by a particular set of design rules, and in extreme cases, cause a short between adjacent lines.
A conventional technique for electrically interconnecting metal features of separated patterned metal layers involves the use of landing pads or "borders." Landing pads are metal forms, e.g., square shaped, formed at locations at a metal level to enable connections to metal features on the same or lower metal levels. Landing pads are typically larger than their associated metal lines to ensure that a good electrical connection is made to the metal lines. Landing pads also provide better control over an etch process used to form vias by reducing the chance that the etch process will remove material beyond the landing pads.
Despite the benefits that landing pads provide, their relatively larger size can adversely affect device performance. First, landing pads can increase the density of metal layers since they are larger than metal lines. The separation between metal lines at locations of landing pads must be greater than locations with no landing pads since the landing pads extend beyond the metal lines. In addition, the relatively larger size of landing pads can adversely affect the electrical characteristics of a metal layer, by increasing the capacitance within a metal layer and between metal layers.
Another technique used in the formation of interconnects between metal layers involves the use of "borderless vias" or "non-nested vias" which provide electrical connections between metal layers without using landing pads. The use of borderless vias to connect metal layers avoids the undesirable characteristics associated with landing pads; however, it is very difficult to print these very small metal islands. For example, if the etched through-hole does not squarely hit the anti-reflective coating on top of a metal line, the resistance of the via rises dramatically.
Based on the performance considerations associated with metal interconnects and the limitations in the prior approaches for connecting metal layers in semiconductor devices, there is a need for an improved technique for electrically connecting metal layers.